The present invention relates to a method of forming a semiconductor device, and more particularly to a method of forming a semiconductor device having a titanium salicide shallow junction diffusion layer.
High integration of a semiconductor device has been made by scaling down semiconductor elements.
For scaling down of the semiconductor elements, it is important to shallow the junction depth of diffusion regions such as source/drain regions or emitter regions. Further, it is also important to reduce an effective sheet resistance as the depth of the diffusion layers is reduced. For those purposes, the titanium salicide diffusion layers have been on the use, wherein a titanium silicide layer having a C54 crystal structure is provided by use of self-alignment technique. Under 0.25 micrometers design rule, the junction depth of the diffusion layer is 0.15 micrometers. Such shallow junction diffusion layer may be formed by an ion-implantation of a conductive impurity. Notwithstanding, it is difficult to form a shallow junction diffusion layer having a junction depth of less than 0.15 micrometers by use of normal ion-implantation of a conductive impurity. Particularly, it was difficult to form a p.sup.+ -type diffusion layer. For example, it was difficult to form a shallow diffusion layer of a junction depth of approximately 0.08 micrometers required under 0.13 micrometers design rule. Also it is required by a normal ion-implantation to form an n.sup.+ -type shallow junction diffusion layer having a depth of approximately 0.05 micrometers required under 0.1 micrometer design rule.
The cause of difficulty in forming such extremely shallow diffusion layers by ion-implantation of the conductive impurity is in a channeling phenomenon in ion-implantation process. Theoretically, at a high dose of ions, silicon substrate surface is made amorphous so that the channeling phenomenon is prevented. Actually, however, the channeling phenomenon appears within an initial time period of the ion-implantation without the silicon substrate surface being made of amorphous.
A conventional method of forming a diffusion layer with avoiding such channeling phenomenon is disclosed in IEEE, Transaction-of-electron-devices, ED-38, pp. 476-486. In accordance with the conventional method, before the ion-implantation of conductive impurity is carried out, an ion-implantation of Ge has been carried out into a predetermined region of the diffusion layer of an n-type silicon substrate surface for forming an amorphous silicon. Subsequently, an ion-implantation of B or BF.sub.2 is carried out. Further, a rapid thermal anneal is carried out at a temperature of 1050.degree. C. to form a p.sup.+ -type shallow having approximately 0.1 micrometer. In the above conventional method, in place of Ge, Si may be ion-implanted.
It is possible to form the shallow junction diffusion layer by use of the above method. However, the channeling phenomenon is likely to be caused by the ion-implantation of Ge or Si for forming the amorphous silicon. Those diffusion layers increase in junction leakage probability as compared to the normal ion-implantation of conductive impurity. Such junction leakage is caused by residual crystal defects due to insufficient recovery of crystal structure from amorphous structure.
It is disclosed in 1987 Applied Physics Letter Vol. 51, No. 12, pp. 1182-1184, that an amorphous silicon layer is formed on a silicon substrate surface to form a diffusion layer over the amorphous silicon layer before a C49 structured crystal phase titanium silicide layer is formed by self-alignment over the diffusion layer. A heat treatment to the C49 structured crystal phase titanium silicide layer is then carried out to cause a phase transition from C49 to C54 thereby forming a C54 structured crystal phase titanium silicide layer. As a result, the crystal defects generated by the formation of amorphous layer are reduced. The junction leakage is reduced by the reduction of the crystal defects. It was measured that p.sup.+ -n junction is in the order of 1.times.10.sup.-8 A/mm.sup.2 or 10 nA/mm.sup.2. The actually required device more scaled down than 0.25 micrometers design rule is approximately 1.times.10.sup.-10 A/mm.sup.2 or 100 pA/mm.sup.2. It is therefore difficult to make a direct combination of the above described two techniques in order to form a titanium salicide shallow diffusion layer.
In the above circumstances, it had been required to develop a novel method of forming a titanium salicide shallow junction diffusion layer while keeping a reduced sheet resistance and avoiding any increase in p-n junction leakage.